1. Field of the Invention
This invention relates to a method for reducing the effect of the parasitic bipolar transistor formed in both high-side and low side LDMOS devices in a multi-phase or polyphase bridge configuration.
2. Brief Description of the Prior Art
A standard H-bridge configuration as shown in FIG. 1 is a circuit for a single phase having at least a first pair of transistors 1, 3 coupled in series and coupled across a power supply having a power rail (+) and a ground rail (xe2x88x92) and a second pair of transistors 5,7 coupled in series and coupled across the same power supply with a load 9 being coupled between the junctions of the transistors of each transistor pair. The transistor of each transistor pair which is coupled to the power rail (+) is referred to as the high side device and the other transistor of each transistor pair which is coupled to the ground rail (xe2x88x92)is referred to as the low side device. In the event plural phases are required, an additional transistor pair is provided for each phase as is well known and shown in phantom in FIG. 1.
With reference to FIG. 2, there is shown an implementation of either one of the transistors of a transistor pair in the circuit of FIG. 1 as an integrated circuit. The circuit is known as a polyphase bridge circuit and the switches generally used are known as reduced surface electric field (RESURF) DMOS transistor/switches, though any type of switch can be used, this application being specific to RESURF DMOS as switches. The circuit includes an n-type buried layer 11 over a pxe2x88x92-type substrate 10 beneath a p-type epitaxial layer 13 into which the transistors are fabricated. The n-type buried layer 11 provides isolation between the transistor thereabove and other transistors on the same chip in conjunction with an n-type sinker or back gate contact 15 which is provided and which passes from the device surface through the epitaxial layer 13 to the buried layer 11. An n-type well region 17 is formed in a part of the epitaxial layer extending to the surface with the remainder of the surface remaining p-type. An n+ contact 19 is provided in the n-type well 17 to provide a drain region and an n+ type region 21 is formed at the surface of the p-well region 20 within the p-type region 13 to provide a source contact and region. An oxide layer 23 is deposited over a portion of the n+ contact 19 and a part of the well region 17 with a polysilicon gate 25 formed over a portion of the n+ source contact 21, the well region 17, any remaining unexposed portion of the well region 17 along the channel and over a portion of the oxide layer. The p+ region 27 within the n-type region 21 is present to provide a backgate contact which is the contact to the p-type region 13.
A problem with the structure as shown in FIG. 2 is that bipolar transistor structures are present in addition to the LDMOS transistors, the bipolar transistors providing parasitics in both the high side and low side LDMOS transistors. In the high side device, there is a pnp transistor between the p-type epitaxial layer 13, the n-type buried layer 11 and the p-type substrate 10 on which the buried layer rests as well as an npn transistor between the n-type drain 17, the p-type epitaxial layer 13 and the n-type buried layer 11. In the low side device, there is a pnp transistor between the p-type epitaxial layer 13, the n-type buried layer 11 and the p-type substrate 10 as well as an npn transistor between n-type drain 17, the p-type epitaxial layer 13 and the n-type buried layer 11. It is these transistors which provide the above-discussed undesirable parasitics
In order to minimize parasitics, the parasitic devices, which are the bipolar transistor configurations, are connected in a manner whereby they do not affect the H-bridge circuit operation in any major way. It is always desirable that these parasitic devices be of as poor quality as possible, this meaning that the gain of these parasitic bipolar transistors should be as low as possible without sacrificing the xe2x80x9coptimizationxe2x80x9d of the main devices of the H-bridge circuit.
In accordance with the present invention, the above noted problem is minimized with the effect of parasitics being reduced relative to the prior art H-bridge structure.
xe2x80x9cBriefly, the improvement is provided by altering the prior art circuit of FIG. 2 with the incorporation of a double buried layer having an n-type buried layer region as in the prior art as well as a p-type buried layer region over the n-type buried layer region, this being for both high side and low side devices and providing an n-type sinker to the n-type buried layer and connecting the sinker/n-type buried layer to the source terminal for the device. This means that, for a high side device, the sinker/n-type buried layer will be connected to one end of the load and, for the low side device, the sinker/n-type buried layer will be connected to the negative terminal of the power supply. In the prior art, the sinker is coupled to the drain in the high side devices. In accordance with the present invention, the sinker is connected to the source for both the high side and low side devices to decrease the bipolar parasitic effects.
In this case, the high side devices have to have their own n+ vertical diffusion for isolation. The advantage of this type of connection for the high side is that a p-type epitaxial substrate can be used because the pnp transistor to the substrate will have a Vbe=0 and will never be active. Also, the design of high side and low side devices as far as coimplanted or double diffused p-type buried layer is concerned is identical. The effect of parasitics in the low side LDMOS devices is to tie the n+ buried layer of FIG. 2 to the source via the sinker with the source being connected to ground and also to have a double-diffused (or coimplanted) p+ buried layer. The sinker is provided by a vertical n+ deposition which also separates the p-type epitaxial layer of the two devices of a transistor pair to reduce the gain of the bipolar transistor formed between the drains of the two low side devices. The gain of this bipolar junction transistor (BJT) can be high due to neutral base width reduction which is more especially for high voltage devices at high voltages. This vertical n+ deposition diffuses into the underlying n+ buried layer and is connected to the source, which is grounded.
It should be understood that all of the vertical depositions forming the sinker surround the entire device, both low side and high side. This arrangement is present to reduce crosstalk between adjacent devices by reducing the gain of the parasitic bipolar transistors formed between adjacent devices and between the DMOS device and other circuitry.
The above described method of laying out an H-bridge with a double diffused or coimplanted p+ buried layer for low side and high side devices and the isolation using properly connected n+ layers is novel and has not been considered in prior analyses of the above noted problem. Furthermore, the addition of a second buried layer of opposite conductivity type to the standard buried layer of the prior art and between the standard buried layer of the prior art and the epitaxial layer of opposite conductivity type over the buried layer, which is more heavily doped than the epitaxial layer, aids in reduction of the bipolar gain of the transistor formed between the buried layer of the prior art, the epitaxial layer thereover of the prior art and the source/drain region of the same conductivity as the buried layer of the prior art and is hence beneficial. Other advantages of the above described solution to the problem of parasitics are reduced die area requirement for isolation of the devices in an H-bridge configuration, reduced effect of the parasitic bipolar devices (including reduced gain) on the operation of the main circuit and cost reduction due to elimination of the need of a p+ substrate (a p-epitaxial wafer is sufficient).